Design and Test of Error Control Decoders in Analog Cmos

Error control decoders are widely used in communication applications. Analog CMOS implementations of error control decoders may outperform digital implementations in portable applications where power is limited. However, there have been little circuit level analyses of analog decoder designs. This dissertation covers the related analog circuits in the decoder design based on the extended (8, 4) Hamming code decoder design. The decoder utilizes a serial input/output interface with a pipelined architecture. It receives the analog signals serially and then processes the data in parallel, finally returning the hard decision serially. The decoder’s performance is analyzed along with the possible effects of mismatch. A decoder chip is manufactured in 0.5μm CMOS technology and the real test data of the analog decoders are provided for the first time. The subcircuits comprising the error control decoder include sample-and-hold circuits, comparators, and basic computational cells. This dissertation presents various designs for these circuits and explores the pros and cons of each. The trade-offs among noise, power, speed and area are studied for each analog circuit. Different decoder requirements may require different subcircuit designs. The analog circuits are simulated using SPICE and also manufactured in test chips with the same 0.5μm CMOS technology. Experimental results on these fabricated circuits are used to validate our analytical and simulation results.